Circuit simulation assisting Physical Fault Isolation for effective root cause analysis

Significance 

The increase in need for quick failure analysis processes and immediate rectification is in tandem with the rapid growth being witnessed in the semiconductor industries. These industries require the utmost level of quality and efficient product development process at minimal costs. Unfortunately, as with most intricate fabrication processes, failure is inherent irrespective of the production phase. To overcome this shortcoming, powerful failure analysis tools and techniques have to be developed and technical knowledge availed for such purposes. Recently, the simulation assistance, physical fault isolation, has been seen to benefit failure analysis engineers tackle more efficiently the root cause of the isolated letdown. However, for analog circuits, the physical fault isolation engineers should be hands on and within the failure analysis facility for them to narrow down the root cause.

Dr. Mahyar Boostandoost and colleagues at Dialog Semiconductor GmbH in Germany proposed a study on circuit simulation assistance of Physical Fault Simulation for effective root cause analysis. The researchers hoped that the results of Physical Fault Simulation analysis and the circuit simulation would provide a better understanding about the device performance under the failed condition and the state of the suspicious circuit at the transistor level. Their work is now published in the research journal, Microelectronics Reliability.

In their study, the researchers employed the non-destructive Photoelectric Laser Stimulation-based technique to change the electrical state of the Device under Test from fail to pass. In this technique, a laser with the wavelength in the Near Infrared range was used to stimulate the analog circuit block at the transistor level and change the device electrical state from fail to pass. The research team then evaluated the circuit behavior at failed condition and verified the failure.

The authors observed that by stimulating the channel of floated-gate transistors, their Vth were decreased and therefore the applied gate voltage could make the channel under the gate thereby enabling them to force the transistors to switch on and consequently reset the output. They also noted that as soon as the laser was turned off or repositioned, the current consumption increased to the initial value in the failure mode.

Mahyar Boostandoost and colleagues study successfully presented novel analog circuit simulation assisting Photoelectric Laser Stimulation-based Physical Fault Isolation technique. They have shown that this new method can be successfully implemented to modify and evaluate the performance of suspicious analog circuit blocks. More so, they have demonstrated the benefits ripped from circuit analysis and simulation assisting Physical Fault Isolation in selecting and approaching the most efficient tools and technique to identify the failure root cause and correct it. This way the competent combination of Physical Fault Isolation and analog circuit simulation can successfully lead us to the corrective action which will in turn improve the circuit design and overcome the inevitable fabrication process variations.

Circuit simulation assisting Physical Fault Isolation for effective root cause analysis. Advances in Engineering

Circuit simulation assisting Physical Fault Isolation for effective root cause analysis. Advances in Engineering

About the author

Mahyar Boostandoost

Since November 2013, I have worked as a Principal fault isolation engineer at “Dialog Semiconductor”, one of the world-class innovative high-tech microelectronics companies.  I coordinate and perform electrical and physical fault isolation techniques as well as necessary sample preparation to enable subsequent physical failure analysis in order to determine the root cause of failures in complex analog and mixed-signal ICs. My ultimate aim has been to use my device physics, circuit design, logic design knowledge and good problem solving skills to identify the failure root cause. I led several projects to optimize the failure analysis process in the area of fault isolation. Successfully, I could introduce new fault isolation tools and develop the most advanced fault isolation methodologies to the standard Dialog failure analysis process to cover the upcoming technology and test challenges.

From 2008 till 2013, I worked as a research fellow at the Technical University of Berlin, one of the leading universities in microelectronics. In March 2013, I finished my Ph.D. at the department of semiconductor devices with the degree of magna cum laude and I published 11 papers in the photovoltaic and failure analysis journals and symposiums.

I made my master in microelectronics in Technical University Chemnitz, in Germany. During my master study at Technical University of Chemnitz, I worked as a member of the AMD student taskforce organized by AMD Dresden. Two years of cooperation in a R&D project related to the future structure of advanced MOSFET transistor, motivated me to continue my study and make carrier in semiconductor industry.

Reference

M. Boostandoost, D. Gräfje, F. Pop. Circuit simulation assisting Physical Fault Isolation for effective root cause analysis. Microelectronics Reliability 76–77 (2017) 194–200

 

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