Top-down fabricated Ge based reconfigurable transistor

Significance 

Conventional integrated circuit (IC) devices do not permit circuit reconfiguration because their logic functions are generally fixed by their physical layout and doped regions. Course-grain reconfiguration is the main approach currently used to overcome this limitation. Unfortunately, this approach is disadvantageous as it does not utilize some active chip regions, leading to high data transfer latency. Fine-reconfiguration has resulted in the required paradigm change allowing the redesign of circuits and devices after manufacturing as well as at runtime. Thus, combinational circuits realized through reconfiguring complete logic blocks exhibited benefits in terms of area and power consumption.

The concepts of conventional field-effect transistors (FETs) are generally limited to static electrical functions primarily because they require extraordinary reproducible and steep doping concertation. With most ICs reaching their physical scalability limits, doping-free reconfigurable FETs (RFETs) have emerged as promising device concepts. As the basic building blocks of such devices, RFETs can dynamically modify the operation of the device between n- or p-type even during runtime. RFETs have been achieved using different channel materials.

Among the available channel materials, Ge has emerged as a potential channel material for reducing the power consumption and solving the switching delay associated with RFETs owing to their reduced bandgap. However, this technology is limited to bottom-up demonstrators where patterning, positioning, nanowire size and crystal orientation control are challenging. Besides, the devices suffer from inherent process variability resulting in different barrier heights and electrical properties. Therefore, developing effective top-down Ge RFET technology to realize the deterministic capability and low variability required to manufacture demonstrator circuits is highly desirable.

Despite Ge being identified as a promising channel material to enable reduction of power consumption and switching delay compared to Si reconfigurable field-effect transistors (RFETs), Ge based devices have been limited to simulations and bottom-up demonstrators not compatible with complex circuit technology. A key material aspect that had been missing so far to advance this prominent technology were the unstable phases upon germanide crystal contact formation,1 that yield in a large variability and unpredictability in the electrical characteristics of the built devices. Thereto, transferring monolithic Al-Ge-Al heterostructures to a deterministic top-down fabrication scheme based on a Ge on insulator (GeOI) platform,2 enabled Ge RFETs with a stable contact crystal phase and abrupt interfaces ensuring a reliable and reproducible contact formation.3 Moreover, the GeOI approach allows the realization of more sophisticated solutions applicable in industrial environments for the implementation of RFET circuits to extend common CMOS capabilities.

Herein, a team of researchers from TU Wien: PhD candidate Raphael Böckle, Dr. Masiar Sistani, and Professor Walter M. Weber designed a deterministic top-down Ge RFET technology to realize a Ge-based RFET architecture. This technology was developed by employing a GeOI integration scheme. Unlike conventional methods that use Ni-germanide contacts, this technology used monolithically integrated Al-Ge-Al heterostructures. The work is currently published in the research journal, Advanced Materials Technology.

The research team findings showed that the new technology was capable of controlling the polarity and suppressing the leakage current due to the injection of specific charge carriers through the gated Al-Ge heterojunctions and the presence of an electrostatic energy barrier. The monolithically integrated Al-Ge-Al heterostructures overcome the challenge of reproducibly and deterministically defining the metallic phase of the drain junctions, thus solving the phase stability issues associated with the conventional methods. Additionally, the Al-Ge exchange produced pure and highly conducting leads. The concentration of the charge carrier in the Ge channel was effectively controlled by the dedicated gate-control, allowing the transistor to be switched on and off. Furthermore, compared with conventional FET architectures, the proposed architecture reduced the off-current significantly while suppressing the ambipolar operation even at elevated temperatures.

In summary, the researchers demonstrated the effectiveness of a three-independent gate RFET scheme based on monolithic Al-Ge-Al heterostructure lodged in a GeOI platform. By tuning the barrier transmissibility, both unipolar n- and p-type operations were successfully achieved. In addition, the use of monolithic Al/Ge contacts reduces the impact of process variability than Ni-germanide contacts. In a statement to Advances in Engineering, the authors explained the new platform provides the initial step towards future generation of adaptable and flexible circuit design based on RFET architecture and will enable alternative and diversified computing approaches.

Colored SEM image of a Ge nanosheet based TTG RFET - Advances in Engineering

Figure legend: Colored SEM image of a Ge nanosheet based TTG RFET

About the author

Masiar Sistani holds a PhD in electrical engineering. In 2019, he defended his PhD thesis entitled “Transport in ultra-scaled Ge quantum dots embedded in Al-Ge-Al nanowire heterostructures” at the Institute of Solid State Electronics, TU Wien with distinction. His doctoral research was focused on the electrical, optical and plasmonic properties of Ge nanostructures with the goal to provide a platform for the exploration of ultra-scaled metal-semiconductor heterostructure devices based on Ge and Ge/Si core/shell nanowires. Starting with 2020, he joined the emerging nanoelectronics devices group of Prof. Walter M. Weber at the Institute of Solid State Electronics, TU Wien. His current research is focused on the integration of Si and Ge nanostructures into reconfigurable transistors to enable adaptive computing.

About the author

Raphael Böckle is a PhD student at the Institute of Solid State Electronics, TU Wien. His research focuses on the exploration of Si and Ge device architectures and their electrical transport properties. In July 2021, he completed his Master thesis, entitled “Ge-based reconfigurable transistors: a platform enabling negative differential resistance“. His current research focuses on the electrical properties of (hyperdoped) metal-semiconductor heterostructure devices based on nanowires.

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About the author

Walter M. Weber holds a PhD degree in the field of semiconductor nano-electronics. From 2002 to 2008 he worked in industrial R&D in semiconductor industry in Munich, Germany, first within the Corporate Research Department of Infineon Technologies AG in the Nanodevices Group of L. Risch and Nanoprocesses Group of W. Hönlein and from 2006 at Qimonda AG in the Materials Research Group of H. Riechert. From 2008 to 2019 he relocated to the Nanoelectronic Materials Laboratory – Namlab gGmbH – in Dresden, where he was responsible of planning, setting-up and coordinating the clean room semiconductor processing technology of the newly established laboratory. As a Senior Scientist there, he also built-up and led the research group on “Emerging Devices” dedicated mainly to the development of reconfigurable transistors. From 2012 to 2019 in parallel to his duties at Namlab he acted as a Research Group Leader at the Cluster of Excellence “Center for Advancing Electronics Dresden, CfAED” at TU Dresden, coordinating activities for the advancement of reconfigurable electronics up to the level of circuit enablement and electronic design automation. In 2019, he was appointed as full professor of nano-electronics at the Institute of Solid State Electronics at TU Wien in Vienna, Austria. His current research is the development of nano-electronic transistors, memories and photodetectors for energy-efficient and adaptable Beyond CMOS applications and their integration capability in modern circuits.

References

(1) Marshall, E. D.; Wu, C. S.; Pai, C. S.; Scott, D. M.; Lau, S. S. Metal-Germanium Contacts and Germanide Formation. MRS Proc. 1985, 47, 161.

(2) Wind, L.; Sistani, M.; Song, Z.; Maeder, X.; Pohl, D.; Michler, J.; Rellinghaus, B.; Weber, W. M.; Lugstein, A. Monolithic Metal–Semiconductor–Metal Heterostructures Enabling Next-Generation Germanium Nanodevices. ACS Appl. Mater. Interfaces 2021, 13, 12393–12399.

(3) Böckle, R.; Sistani, M.; Lipovec, B.; Pohl, D.; Rellinghaus, B.; Lugstein, A.; Weber, W. M. A Top‐Down Platform Enabling Ge Based Reconfigurable Transistors. Adv. Mater. Technol. 2022, 7, 2100647.

Go To Adv. Mater. Technol.

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