A Possible Solution for Next Generation 3-D IC’s Thermal Challenge

Transistor-level 3D integrations such as monolithic 3-D, Skybridge, and SN3D are promising approaches for enhancing future IC scaling. These 3-D architectures, however, face thermal management challenges attributed to lack of heat dissipation paths and stacking of the transistors. Past reviews of the traditional system-level thermal management approaches like forced air cooling have revealed their inability to effectively manage thermal problems all levels of integration more so at the circuit level.

To address this, the authors: Md Arif Iqbal, Naveen Kumar Macha, Wafi Danesh, Sehtab Hossain and led by Dr. Mostafizur Rahman from the University of Missouri-Kansas City previously introduced a concept on heat management in 3-D ICs based on architecting physical fabric features. Herein, they aimed at expounding on their previous work to elaborate on the thermal management approaches and its benefits. In particular, they demonstrated its application in the transistor-level 3-D ICs using finite element method-based modeling and simulations. Their work has been published in the Microelectronics Journal.

Their proposed concept was based on generic 3-D thermal management features allowing for both static and dynamic thermal modeling taking into account the device-specific materials, circuit operating conditions, and circuit layout. To begin with, a device-level analysis was first performed then expanded to the circuits. Eventually, a finite element based thermal evaluation of 3-D circuits under different operating conditions was conducted.

The authors observed the material stacking and dielectric effects on the final thermal profile of the 3D integrations. Without heat extraction features, a temperature increase was reported in monolithic 3-D, Skybridge and SN3D by 100K, 300K and 50K respectively. Nonetheless, the proposed heat extraction feature proved very effective for heat management applications by reducing the temperatures to almost by half to achieve the normal operation temperature. This was attributed to the ability of the finite element modeling method to account for the material properties, nanoscale effects, 3-D layouts, and 3-D circuit style. Even though the temperatures did not drop instantly due to thermal contact resistance at the extraction interface, the heat extraction features were flexible and could be placed anywhere in the circuit without jeopardizing the circuit operation.

In summary, the research team carried out extensive simulations to determine the dynamic and static thermal profile of 3-D transistor base circuits to evaluate the effectiveness of heat extraction features in thermal management and mitigation. Thermal behaviors of different transistor-level 3-D integration were simulated with and without heat extraction features and a comparison of the two results was discussed. The inclusion of heat extraction features resulted in a heat temperature reduction by 27%-48% and thus exhibited a promising approach for maintaining ambient circuit operation temperature. In a statement to Advances in Engineering, Dr. Mostafizur Rahman, the lead author commented that the uniqueness of the heat management approach presented in this study is key and will open new opportunities for 3-D circuit integration.