Comprehensive reliability and aging analysis on SRAMs within microprocessor systems

All electronic circuits degrade during operation. Eventually, the degradation is so large that it causes the circuits to no longer function properly.  Most customers of electronic devices expect at least a 10 year lifetime.  Manufacturers currently do qualification testing via accelerated life testing using manufactured samples of prototype circuits. Failures of qualification tests entail additional re-design engineering costs and the cost of re-fabrication.  In addition, qualification failures impact time-to-market, often delaying new product releases by many months.  Together, these costs add up to millions of dollars for individual companies and hundreds of millions of dollars annually across the semiconductor industry.  The toolset will check if the memory in a design can meet lifetime requirements prior to the manufacturing and will provide guidance to improve the lifetime of the memory array in a microprocessor system.

A framework is proposed to analyze the impact of both Front End of the Line (FEOL) and Back End of the Line (BEOL) wearout mechanisms on memories embedded within state-of-art microprocessors. Our methodology finds the detailed electrical stress and temperature of each SRAM cell within a memory by running a variety of standard benchmarks. Combining the stress/thermal profiles and the wearout models, the performance degradation of SRAM cells for each wearout mechanism is studied. The lifetimes of the SRAM cells are then obtained when the performance metric degrades to a predefined threshold. The proposed work introduces a method to deal with the large volume of SRAM cells whose stress is non-uniform by partitioning the SRAM cells into different stress states, and generates the lifetime distribution of the memory system due to each wearout mechanism by combining the lifetimes of the cells, whose distributions vary with the stress received. Seven wearout mechanisms have been studied, namely, negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), hot carrier injection (HCI), gate oxide breakdown (GOBD), backend dielectric breakdown (BTDDB), electromigration (EM), and stress-induced voiding (SIV).

Since the wearout mechanisms being studied are activity and temperature dependent, the proposed framework determines the detailed thermal profile of the memory under study, as well as the electrical stress of each net/device in the memory. Combining these profiles and wearout models, the performance degradations of the SRAM cell are studied. In this paper, four performance metrics are considered: read and retention static noise margins (SNMs), write margin, read current (IREAD), and the minimum retention voltage (Vdd-min). When any of these four performance metrics degrade to a pre-defined threshold, the SRAM cell is said to have failed and thus the lifetime of this cell is obtained. In order to deal with the large volume of SRAM cells in a memory all of which receive different stresses, the cells are partitioned into 21 different stress states, where the cells in each stress state receive the same stress. By this method, the lifetimes of all the cells in the memory due to each wearout mechanism are determined. Moreover, the lifetime estimates take into account realistic use scenarios which include active, standby, and sleep modes.