Multisampling Asymmetric Dual-Edge DPWM for Improved Dynamic Performance in Power Electronics

Digital control systems have become the standard in various power electronics applications, replacing analog systems due to their superior flexibility, programmability, and resilience to environmental variations. However, despite these advantages, digital systems are often hampered by phase delays introduced by components such as analog-to-digital converters, finite sampling frequencies, algorithm computation times, and notably, digital pulsewidth modulators (DPWMs). These delays can adversely affect the dynamic performance and stability of control systems, particularly in high-performance applications where response time is critical. In traditional DPWM systems, the delays are often mitigated through multisampling techniques, where the number of samples per modulation cycle is increased to improve resolution and dynamic response. However, these techniques are not without their drawbacks. The introduction of higher sampling rates can lead to nonlinearities, noise amplification, and other issues that degrade system performance. Moreover, the effectiveness of these techniques is limited by the inherent operating point dependence of the modulator, which can result in inconsistent performance across different operating conditions. In recent years, alternative DPWM architectures have been proposed to address these issues. Among them, the Asymmetric Dual-Edge (ADE) carrier-based DPWM has shown promise in eliminating phase delay and even introducing positive phase gain. These advancements suggest that further improvements in dynamic performance could be achieved by combining ADE-DPWM with multisampling techniques. However, the potential benefits of such an approach have been limited by the operating point dependence inherent in ADE-DPWM architectures.

New study published in IEEE Transactions on Power Electronics and conducted by Dr. Giovanni Bonanno; Andrea Comacchio and led by Professor Paolo Mattavelli from the University of Padua in Italy, reachears introduces a novel multisampling ADE-DPWM architecture that addresses these challenges, offering a comprehensive design approach that mitigates operating point dependence while harnessing the benefits of multisampling. The proposed architecture is thoroughly analyzed, both theoretically and experimentally, to validate its performance and compare it with state-of-the-art TTE-DPWM systems. The proposed multisampling ADE-DPWM architecture is designed to eliminate the typical delays found in traditional DPWM structures. To highlight its advantages, the study begins by comparing the ADE-DPWM with the state-of-the-art TTE-DPWM. The TTE-DPWM is a widely used approach in digital control systems, known for its simplicity and effectiveness in reducing phase delay through double-sampling techniques. However, it is not without limitations, particularly when it comes to operating point dependence and the non-linearities introduced by higher sampling rates. In contrast, the ADE-DPWM architecture offers a more flexible approach, where the modulation period is dynamically adjusted based on the modulating signal. This dynamic adjustment allows for independent control of the on and off phases of the DPWM, resulting in a more pronounced and consistent response to changes in the modulating signal. The study provides a detailed comparison of these two architectures, both qualitatively and analytically, demonstrating the superior performance of the ADE-DPWM in terms of phase delay and dynamic response.  Building on the basic principles of ADE-DPWM, the authors introduces an enhanced multisampling architecture designed to further improve dynamic performance and mitigate operating point dependence. The proposed architecture is based on the concept of sampling the modulating signal multiple times per modulation cycle, with each sample contributing to the final modulation period. This approach allows for a finer resolution in the modulation signal and a more accurate representation of the system’s dynamic behavior. One of the key challenges addressed by the proposed architecture is the operating point dependence that arises when the number of samples per cycle exceeds two. In traditional ADE-DPWM systems, the operating point dependence can lead to inconsistent performance across different operating conditions, particularly at higher sampling rates. The study proposes a novel solution to this problem by introducing additional terms in the modulator’s transfer function that account for variations in the modulating signal across the entire modulation period. These additional terms are carefully designed to minimize the impact of operating point dependence while maximizing the phase gain introduced by the ADE-DPWM architecture.

The researchers provides a detailed analysis of the proposed architecture, including a formal definition of the multisampling factor and a comprehensive mathematical model that describes the time-domain evolution of the modulator’s output. This model serves as the foundation for the small-signal analysis presented in the following section, which validates the effectiveness of the proposed architecture in improving dynamic performance and mitigating operating point dependence. The small-signal analysis of the proposed multisampling ADE-DPWM architecture is conducted using the describing function (DF) method, a well-established technique in control theory for analyzing the frequency response of non-linear systems. The study derives the small-signal transfer function of the ADE-DPWM architecture, which provides valuable insights into its behavior across different operating points and sampling rates. They validated the small-signal model through extensive experimental testing, which involves superimposing small sinusoidal perturbations on the modulating signal and measuring the resulting frequency response of the modulator. The experimental results are compared with the theoretical predictions, confirming the accuracy of the small-signal model and demonstrating the superior performance of the proposed architecture in terms of phase gain and operating point independence. They also performed sensitivity analysis, which explores the impact of various system parameters on the modulator’s performance. This analysis provides valuable guidelines for optimizing the design of ADE-DPWM systems, particularly in terms of selecting appropriate weight functions for the additional terms introduced in the transfer function. The results of this analysis highlight the importance of careful tuning of these parameters to achieve the desired balance between dynamic performance and operating point independence.  The proposed multisampling ADE-DPWM architecture is validated through extensive experimental testing, which is conducted using a custom-built testbed equipped with a Xilinx XC7Z030-3FBG676E FPGA. The experimental setup allows for precise control of the modulating signal and accurate measurement of the modulator’s output, enabling a thorough evaluation of the proposed architecture’s performance. The experimental validation includes over 1000 individual tests, covering a wide range of operating points and sampling rates. The results of these tests confirm the superior dynamic performance of the ADE-DPWM architecture compared to state-of-the-art TTE-DPWM systems, particularly in terms of phase gain and response time. The study also demonstrates the robustness of the proposed architecture against operating point variations, highlighting its potential for use in a wide range of power electronics applications.

In conclusion, Professor Paolo Mattavelli and his colleagues introduced a novel multisampling ADE-DPWM architecture that addresses the limitations of traditional DPWM systems. The proposed architecture offers superior dynamic performance and robustness against operating point variations, making it a promising solution for high-performance applications where response time and stability are critical. Moreover, the comprehensive analysis and experimental validation conducted in this study provide valuable insights into the design and optimization of ADE-DPWM systems, offering a solid foundation for further research and development in this area. The proposed architecture represents a significant step forward in the field of digital control systems, with the potential to revolutionize the way DPWM is implemented in power electronics applications.