Technological advances in the field of integrated circuits and semiconductors have led to the development of complementary metal oxide semiconductors (CMOS) with applications in numerous areas including memory devices. Currently, the design and development of non-volatile memory devices are based on current technologies. Alternatively, recent research has shown that numerous problems experienced today are mainly associated with heat, quantum uncertainties and costs of fabrication. As such, due to the physical limitations of the CMOS technologies, researchers have been looking for alternative ways of addressing the problems to develop future generation memory devices.
Consequently, in a recently published literature, resistive switching device has been identified as a promising non-volatile memory thus attracting significant attention of researchers. This is due to its high-density fabrication and capability to replace dynamic random-access memories. Among the available single bit based non-volatile memories, crossbar arrays have particularly demonstrated high-density integrations. Unfortunately, the high-power consumption and sneak current problems that lead to read errors have limited the use of crossbar arrays. Several approaches such as the incorporation of rectifying elements have been proposed to overcome the sneak current problem. Despite the remarkable achievement, more insight is still highly desirable.
To this note, Professor Jinho Bae at Jeju National University together with Professor Nobuhiko Kobayashi at the University of California Santa Cruz developed a new design parameter to perform an error analysis in passive crossbar arrays. Specifically, the sneak current problem was investigated by connecting the memory cell to a pair of row-column in either high resistance or low resistance depending on the stored logic value. The study is currently published in the journal, Semiconductor Science and Technology.
In brief, the research team initiated their work by a detailed cross-examination of the influence of the resistive switching behavior on the forward current flow in low resistance state and reverse current flow in the high resistance state along sneak current paths. Next, the ratio of the reverse low resistance state to forward low resistance state was maximized and its influence on the miss read error and sneak current investigated.
The authors observed minimal sneak currents in the resistive switches connected in reverse bias. This was attributed to the use of asymmetric memristors that fairly blocked the reverse current. On the other hand, maximizing the newly proposed parameter, that is, the ratio of reverse low resistance state to forward low resistance state also contributed significantly to minimizing the sneak currents. Furthermore, it was worth noting that the sneak current problem was more in large size arrays than small size arrays. This was, however, reduced by having the read current dominate the sneak current.
In summary, for commercialization of crossbar resistive switching arrays, Jinho Bae and Nobuhiko Kobayashi proposed two main design points to be taken into consideration. This includes the design parameter, reverse low resistance state to forward high resistance state ratio, and the read error bound. Altogether, the resistive switching devices is a promising solution for large scale design and production of high-performance non-volatile random-access memories.
The work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (NRF-2016R1A2B4015627).
Bae, J., & Kobayashi, N. (2019). Resistive switching device with highly-asymmetric current-voltage characteristics: its error analysis and new design parameter. Semiconductor Science and Technology, 34(2), 025007.Go To Semiconductor Science and Technology