Tapered self-written waveguide for a silicon photonic chip I/O


The impressive advances in artificial intelligence, disaggregated computing and high-performance computing applications have necessitated increasing datacenter bandwidth and reducing energy consumption without compromising high-performance capabilities. While larger datacenter bandwidth could be enhanced by optical interconnects by silicon photonics (SiPh), co-packaged optics (CPO) technology, where optical devices are implemented close to electric devices, can achieve both energy consumption reduction and high bandwidth. To this end, incorporating CPO with SiPh has emerged as a promising candidate for realizing high-bandwidth and low-energy consumption optical interconnects.

Achieving the desired SiPh scalability and cost-efficiency in CPO technology remains a big engineering challenge. It requires accurate submicrometer positioning for low-loss optical coupling and reduction of the coupling loss caused by the mismatch of the mode field diameter (MFD) between standard single-mode fibers and SiPh chips. To address these issues, relaxing the submicrometer-order optical alignment tolerances is necessary for CPO. A self-written waveguide (SWW) is promising candidate for realizing CPO with SiPh because it makes it possible to relax the tight alignment tolerances associated with the optical connections.

While SWWs, specifically tapered SWWs, can reduce the coupling loss caused by the MFD mismatch between the SSMFs and SiPh chips, their use for connections between SSMFs and SiPh is challenging. This can be mainly attributed to the difficulty of using SWWs in silicon waveguides, as the visible light used for curing during SWW formation fails to radiate from the waveguide facet due to material adsorption loss. Developing more effective strategies to overcome this issue is highly desirable as the available approaches, like using resins doped with special dyes and forming SWWs with telecommunication light, still suffer from numerous drawbacks.

Herein, Mr. Yohei Saito, Dr. Kota Shikama, Dr. Tai Tsuchizawa, and Dr. Norio Sato from NTT Device Technology Laboratories proposed a novel method for fabricating tapered SWWs (TSWWs) from a SiPh waveguide facet with visible light. This approach is based on a newly developed optical circuit comprising silicon and silicon oxynitride (SiOxNy) waveguides for SWW formation from SiPh chips. The circuit also consists of spot size converters to aid light coupling. Their work is currently published in the peer-reviewed journal, Optics Letters.

The research team demonstrated the effectiveness and reliability of the newly proposed approach. For example, their method allows the use of reliable visible-light-cured resins like those used in optical communications devices. Using the proposed connection method, it was possible to achieve an optical coupling between the SSMF and SiPh chip via TSWW formation. The normalized loss with the TSWW is about 0.6 dB over a wavelength range of 80 nm without high-accuracy positioning. The TSWW connections exhibited 1-dB alignment tolerances, which were about ±1.4 µm and ±1.6 µm in the vertical and horizontal directions, respectively. Although the reported coupling losses are comparable to butt coupling with high-numerical aperture fiber, the resulting alignment tolerances are higher than those with the butt coupling technique.

In a nutshell, the scientists of NTT Device Technology Laboratories reported the development a new method for tapered SWW formation from silicon photonics chips. The optical circuit designed in this study could satisfy the requirements for SWW connection, including those visible light and telecommunication light emitted from the same waveguide facet. In a statement to Advances in Engineering, first author Mr. Yohei Saito pointed out that their study provided valuable insights that would contribute to highly efficient SWW formation with visible light for advanced SiPh packaging technology.


Saito, Y., Shikama, K., Tsuchizawa, T., & Sato, N. (2022). Tapered self-written waveguide for a silicon photonic chip I/O. Optics Letters, 47(12), 2971-2974.

Go To Optics Letters

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