Wires as Heatsinks: Reducing Thermal Resistance in CMOS-SOI ICs


CMOS silicon-on-insulator integrated circuits (CMOS-SOI ICs) are widely used in different applications, including microwave communication and radar systems, and are currently being actively researched for potential use in 5G mm-wave systems. Generally, self-heating properties and thermal characteristics are some of the most important parameters that must be considered in the design of power amplifier integrated circuits owing to their remarkable influence on the device modeling, performance and reliability. In CMOS-SOI IC technology, thermal resistance is of specific importance as it plays a crucial role in governing the self-heating of the device that could severely degrade the performance of high-power density devices. However, the evaluation of thermal resistance is more complicated for field effect transistors (FETs) in CMOS-SOI technology than for other types of transistors.

CMOS-SOI ICs utilize a buried oxide layer (BOX) underneath the transistor to increase high frequency performance, but this also increases the thermal resistance and can exacerbate the self-heating. Fortunately, the interconnect metals and surrounding oxide also provide additional paths for heat sinking that can mitigate this effect. Therefore, accurate determination of the overall thermal resistance must account for the additional heat flow and heat sinking contributions. Nevertheless, the available techniques for simulating these heat sinking contributions as well as the interconnect effects have several limitations that compromise their applications. For instance, most techniques do not quantify the cross-heating effects, packing effects and dimensional scale effects. Although there are significant research efforts to address these limitations, more studies are still needed. Herein, Ms Sravya Alluri and Professor Peter Asbeck from the University of California San Diego together with Dr. Jefy Jayamon, Dr. Bassel Hanafi at Qualcomm Inc., presented a detailed simulation and experimental measurement of the interconnect effects on the layout-dependent thermal resistance of FETs in CMOS-SOI transistors used in microwave power ICs. They specifically quantified the role of the interconnects in determining the thermal resistance experienced by the power FETs. In their approach, a straightforward simulation technique adapted from a commercial electromagnetic solver (EMX) to heat flow was utilized to simulate the contributions of the additional heatsinking paths. Finally, the simulation results were validated through a series of experiments. Their research work is currently published in the research journal, Solid State Electronics.

The research team showed that the heat flow via interconnects within power FETs accounts for about 50 – 70% of the overall heat flow in the microwave and mm-wave ICs. The analytical results enabled the estimation of various thermal resistance contributions. The interconnect effects reportedly improved the thermal resistance values more than those directly computed from heat conduction via the BOX. These evaluations were enabled by the effectiveness of the simulation technique and its ability to overcome the limitations of the previously used techniques. For example, it enabled the quantification of the cross-heat effects which enhanced the accuracy of the results. Furthermore, guidelines for reducing the thermal resistance, including variations in FET layouts and adjacent structures, were provided in their paper.

In summary, the authors successfully developed a simple simulation technique derived from widely available microwave circuit simulation to simulate the thermal resistance of microwave FETs. The findings of Sravya Alluri and colleagues were used to determine the thermal resistance of CMOS-SOI embedded in power amplifier IC layouts. The experimental results reported through the I-V characteristics of a p-n diode used in monitoring the FET temperature agreed well with the numerical results. In a statement to Advances in Engineering, authors said that the study provided important insights that would contribute to effective mitigation of thermal resistance in FETs, thereby enhancing their performance.

Wires as Heatsinks: Reducing Thermal Resistance in CMOS-SOI ICs - Advances in Engineering
a) Schematic heat flow from FET through buried oxide (yellow) and through interconnecting wires. b) 3D representation of FET and interconnects showing relative sizes in CMOS power integrated circuit.

About the author

Sravya Alluri received her B.Tech degree in Electronics and Communication Engineering from National Institute of Technology Warangal, India in 2015 and her M.S degree in Electrical and Computer Engineering from the University of California San Diego, CA in 2018. She is currently an R&D Engineer at the Qualcomm Institute, UCSD. Her research interests include design of high efficiency millimeter-wave power amplifiers.



Alluri, S., Jayamon, J., Hanafi, B., & Asbeck, P. (2021). Interconnect effects on thermal resistance of CMOS-SOI transistors in microwave power integrated circuitsSolid State Electronics, 186, 108149.

Go To Solid State Electronics

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