Advances in Engineering Advances in Engineering features breaking research judged by Advances in Engineering advisory team to be of key importance in the Engineering field. Papers are selected from over 10,000 published each week from most peer reviewed journals.
Microelectronic Engineering, Volume 109, September 2013, Pages 101-104.
S. Shahabuddin, N. Soin, K.K. Goh, Y. Abdul Wahab, H. Hussin
Silterra (M) Sdn. Bhd., Lot 8, Phase II, Kulim Hi-tech Park, 09000 Kulim, Kedah, Malaysia and
Department of Electrical Engineering, University of Malaya, 50603 Kuala Lumpur, Malaysia and
Center of Electronic Engineering Studies, Faculty of Electrical Engineering, Universiti Teknologi MARA, 40450, Malaysia.
Abstract
The reliability characterization in shallow trench isolation (STI) based n-channel lateral diffused metal–oxide–semiconductor (LDMOS) transistor has recently drawn much attention. A thorough investigation of the hot carrier degradation under various gate and drain stress biases are carried out to gain an insight on the bias dependences of the parameter drifts. The findings are supported by both experimental and the technology computer-aided design (TCAD) simulations data. Based on the results, the drain voltage (VDS) parameter was found as a significant accelerating factor for the test. The analysis of HCI damage phenomenon on this device shows that the degradation mechanism is highly dependent on the stress voltage at the gate (VGS).
