A 2.5-GHz direct digital frequency synthesizer in 0.18 um CMOS

Analog Integrated Circuits and Signal Processing, February 2015, Volume 82, Issue 2, pp 369-379.

Zhang Jun-an, Li Guangjun, Zhang Ruitao, Li Jiaoxue, Wei Yafeng, Yan Bo.

  1. Collage of Communication and Information Engineering, University of Electronic Science and Technology of China, Chengdu, 611731, China and
  2. Key Laboratory of Analog Integrated Circuit, Chongqing, 400060, China.

 

Abstract

A 2.5 GHz direct digital frequency synthesizer (DDS) in 0.18 um CMOS is presented. This DDS has a 32 bit phase word and uses an optimized excess-four Coordinated Rotation Digital Computer (CORDIC) arithmetic to achieve phase to amplitude conversion (SFDR as 113 dB). A time interleaved architecture is used to achieve 2.5 GHz high speed. Fundamental principle of CORDIC and four practical considerations in circuit implementation are also presented. This 2.5 GHz DDS (with an embedded 14 bit current steering DAC) is implemented in a 0.18 um CMOS technology, occupies 4.6 mm × 4.2 mm including bond pads. Measured performance is SFDR >58 dB (spur cancelled) and narrowband SFDR >84 dB for output signal frequencies up to 1 GHz.

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