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Solid-State Electronics, Available online 19 March 2013.
A. Diab, C. Fernández, A. Ohata, N. Rodriguez, I. Ionica, Y. Bae, W. Van Den Daele, F. Allibert, F. Gámiz, G. Ghibaudo, C. Mazure, S. Cristoloveanu
IMEP-LAHC, Grenoble-INP Minatec, BP 257, 38016 Grenoble, France
Department of Electronics, Faculty of Sciences, University of Granada, 18071 Granada, Spain
Osaka City University, Sugimoto, Sumiyoshi-ku, Osaka 558-8585, Japan
Uiduk University, Gangdong, Gyeongju 780-713, South Korea
SOITEC S.A., Parc Technologique des Fontaines, 38190 Bernin, France
Abstract
We demonstrate for the first time the feasibility of split C–V measurements on as-fabricated SOI wafers using pseudo-MOSFET configuration. An adapted methodology to determine the effective mobility of electrons and holes by split C–V technique is proposed and validated through comparison with the effective mobility extracted from static measurements. The method has been applied to different SOI materials (thin and thick film/BOX, passivated and non-passivated surface). The frequency and substrate depletion effects and the role of probe pressure and spacing are discussed. The electron mobility can exceed 500 cm2 V−1 s−1in thin SOI films with passivated surface.
