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M. Finc, A. Zemva
Faculty of Electrical Engineering, Laboratory for Integrated Circuits Design, University of Ljubljana, Trzaska c.25, 1000 Ljubljana, Slovenia
Received 13 April 2004; Accepted 26 July 2004. Available online 7 April 2005.
Abstract
In this paper, we present an efficient approach to profiling for HW/SW partitioning. The execution of arbitrary SW code regions is analyzed with a clock-cycle accuracy without introducing an additional profiling induced performance overhead. Based on the profiling principle, performance analysis of the initial functional SW description and performance estimation of various HW/SW partitioning configurations are systematically and iteratively carried out. For an efficient evaluation of different partitioning possibilities no design and implementation of HW co-processing blocks are necessary. The principle equally covers the simulation and implementation domains. The approach is highly suitable for embedded soft-core SoPC applications. In order to demonstrate its use, we developed a COMET Profiler tool. The design flow is illustrated with two case studies.
