Younes Lahbiba, Romain Kamdemc, Mohamed-lyes Benalycherifc, Rached Tourkib
Electronics and Micro-Electronics Laboratory, Received 28 January 2005; Accepted 13 April 2005., Available online 26 July 2005.
Property specification languages and ABV (assertion-based verification) driven by simulation are being recognized by many as essential for verification of today’s increasingly complex designs. In addition, there are few mature approaches that concentrate on improving assertion integration with high-level designs modeled in SystemC. This paper discusses the issues faced within SystemC environments to incorporate PSL (property specification language) assertions. It also proposes an automatic solution that enhances SOC (system on chip) SLD (system level design) flow with PSL assertions embedded into SystemC designs.
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