Liakot Alia, Roslina Sideka, Ishak Arisa, Alauddin Mohd. Alib, Bambang Sunaryo Suparjoa
Department of Electrical and Electronic Engineering, University Putra Malaysia, Serdang, Selangor 43400, Malaysia, Received 8 October 2002; revised 1 July 2003; Accepted 1 December 2003, Available online 21 May 2004
This paper presents the design of a universal asynchronous receiver and transmitter (UART), which is fully functional and synthesizeable. Due to its modularity, configurability and extremely compact size, the proposed UART is named as micro-UART and it is ideal for system-on-a-chip (SoC) application. The core is usable as an intellectual property. Verilog hardware description language (HDL) in the Altera’s MAX-PLUS II environment has been used for its design, compilation and simulation. The UART has been implemented using Altera’s FPGA technology.
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