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Microelectronic Engineering, Volume 114, February 2014, Pages 22-25.
M.A. García-Ramírez, A.M. Ghiass, Z. Moktadir, Y. Tsuchiya, H. Mizuta.
Nano Research Group, School of Electronics and Computer Science, Faculty of Physical and Applied Sciences, University of Southampton, Highfield, Southampton SO17 1BJ, United Kingdom and
Japan Advanced Institute of Science and Technology (JAIST), Ishikawa 923-1292, Japan.
Abstract
We report the fabrication and characterisation of a suspended double-clamped beam structure that is implemented as a movable control gate within a hybrid high-speed non-volatile memory device. This structure features a foundation of SiO2/Si layers over which a poly-Si layer (sacrificial) is deposited by using a low-pressure chemical vapour deposition (LPCVD) and as a movable control gate, an aluminium (Al) layer is deposited by using an e-beam evaporator. The Al layer is patterned with double-clamped beam structures by using photolithography and through a combination of wet and dry etching processes, the structures are successfully suspended and characterised by using a C–V meter. From the structure characterisation, the pull-in curve is successfully obtained and due to unexpected large short-range forces such as the van der Waals forces, the pull-out curve is not observed. In order to clarify this issue, a numerical analysis is performed in which the structural materials under test shown the influence of such short-range forces on the structure and a solution to override them is proposed.
Additional Information:
Non-volatile memories, such as Flash memory, has an inherent issue on the scaling-down process (Moore’s law) due to its tunnelling oxide layer cannot be thinner than 7 nm. Since it was exposed few year ago by the ITRS, a few research centres as well as the semiconductor industry moved towards new options to be exploited in order to give enough time to the ’emerging technologies’ to reach a maturity level. This is why, we proposed a hybrid structure that encompasses the well known MOS technology with the nano-electromechanical systems (NEMS) in order to create a MOS-NEMS non-volatile memory device.
In here, a MOSFET features a readout element that is isolated from the memory node by a rather thick oxide (SiO2), the memory node is made by a thin monolayer of silicon nanodots that are doubly isolated from the control gate (Al) by a thin tunnel oxide layer (7nm) and by an air gap. By performing numerical analyses, it was found that the programming and erasing operations are performed at ~3 ns, at least 3 magnitude orders higher than the nowadays Flash memory. The Suspended Gate Silicon Nanodot Memory fabrication was challenging. We used a Si substrate on which a high quality SiO2 layer was growth, on top of this we used poly-Si as a sacrificial layer and as a control gate an Al layer (Si\SiO2\Poly-Si\Al).
As a result of the fabrication process, we developed, from scratch, a few recipes in order to suspend the control gate layer. In here, the poly-Si layer was removed by using a single-step dry-etching process without affecting severely the SiO2 and Si layers. When measured, it was found that the suspended gate collapsed when bias, as expected, on the tunnel oxide layer but returned even at voltages lower than pull-in. Further analyses shown that the short-range forces such as the Casimir or van der Waals forces are stronger at lower distances (2 nm) which, in this case, keep attached the suspended gate into the tunnel oxide layer. The magnitude of those forces are double of the Al restoring force. A numerical analysis shown that by using a different suspended gate material such as poly-Si instead of Al, it is found that the restoring force is higher that the short-range forces.
