Gate capacitance modeling and width-dependent performance of graphene nanoribbon transistors

Microelectronic Engineering, Volume 112,  2013, Pages 220-226.

George S. Kliros.

 

Department of Aeronautical Sciences, Division of Electronics and Communications Engineering, Hellenic Air-Force Academy, Dekeleia Air-Force Base GR-1010, Attica, Greece

 

Abstract

The width-dependent performance of armchair GNRs-FETs is investigated by developing a fully analytical gate capacitance model based on effective mass approximation and semiclassical ballistic transport. The model incorporates the effects of edge bond relaxation and third nearest neighbor interaction as well as thermal broadening. To calculate the performance metrics of GNR-FETs, analytical expressions are used for the charge density, quantum capacitance as well as drain current as functions of both gate and drain voltages. Intrinsic gate delay time, cutoff frequency and Ion/Ioff ratio are also calculated for different GNR widths. Numerical results for a double-gate AGNR-FET operating close to quantum capacitance limit show that nanoribbon widths of about 3–4 nm at most are required in order to obtain optimum on/off performance.

 

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Additional Information:

 

We obtained numerical results for a Double-Gate armchair GNR-FET with thin and high-k gate-insulator (e.g. HfO₂) so that the quantum capacitance limit can be reached. The width of GNR is determined by the number N defined by counting the number of C-atoms forming a zig-zag chain in the transverse direction. We have focused on the two armchair GNRs families with N=3p and = 3p+1 where p is a positive integer. We have shown that: a) in order to obtain a ratio I_on/I_off =10⁶, armchair GNR-channel of the family 3p+1 with widths of about 3-4 nm at most are required, b) throughout the bias window, the cutoff frequency f_T exceeds the THz barrier, confirming the excellent high-frequency performance of GNR-FETs.