Reconfigurable gate array architecture for logic functions in tunneling transistor technology

Microelectronics Journal, Volume 44, Issue 8, August 2013, Pages 706–711.

Gerousisa, , , A. Grepiotisb

a Department of Physics, Computer Science and Engineering, Christopher Newport University, Newport News, 23606 Virginia, USA and

b Science Systems and Applications (SSAI) @ NASA Langley Research, Hampton, Virginia 23666, USA.

 

Abstract

This work describes the design of a reconfigurable logic gate array composed of single-electron tunneling (SET) transistors currently under investigation as potential postCMOS candidates for future nano-scale integrated circuits for use in low-power embedded systems. A layer in the proposed array consists of a SET summing-inverter block replicated in subsequent blocks and extended to implement flexible logic functions in terms of the sum-of-products (SoP) and products-of-sum (PoS) forms. The reconfiguring of the array can be accomplished through the alteration of a block’s logic function by way of a control voltage. The reconfigurable array can work normally at room temperature and can flexibly realize functions with better performance at lower power compared with pure MOSFET circuits.

Go To Journal

 

nano-scale integrated circuits

Check Also

Light-Speed Encryption: Unlocking the Future with Spatially Incoherent Diffractive Neural Networks - Advances in Engineering

Light-Speed Encryption: Unlocking the Future with Spatially Incoherent Diffractive Neural Networks