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Microelectronics Reliability, Volume 53, Issues 9–11, September–November 2013, Pages 1183-1188.
Chang-Chih Chen, Fahad Ahmed, Linda Milor.
School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332, USA.
Abstract
A framework is proposed to analyze the impact of negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on memories embedded within state-of-art microprocessors. Our methodology finds the detailed electrical stress and temperature of each SRAM cell within a memory, embedded within a system running a variety of standard benchmarks. We study DC noise margins in conventional 6T SRAM cells as a function of NBTI/PBTI degradation and provide insights on memory reliability under realistic use conditions.
