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A.S. Budiman, H.-A.-S. Shin, B.-J. Kim, S.-H. Hwang, H.-Y. Son, M.-S. Suh, Q.-H. Chung, K.-Y. Byun, N. Tamura, M. Kunz, Y.-C. Joo
Microelectronics Reliability, Volume 52, Issue 3, March 2012
Abstract
Through-silicon via (TSV) has been used for 3-dimentional integrated circuits. Mechanical stresses in Cu and Si around the TSV were measured using synchrotron X-ray microdiffraction. The hydrostatic stress in Cu TSV went from high tensile of 234 MPa in the as-fabricated state, to −196 MPa (compressive) during thermal annealing (in situ measurement), to 167 MPa in the post-annealed state. Due to this stress, the keep-away distance in Si was determined to be about 17 μm. Our results suggest that Cu stress may lead to reliability as well as integration issues, while Si stress may lead to device performance concerns.
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